Conventional flip-chip integrated circuit devices include a grid array of contact pads for electrically and mechanically connecting the flip-chip integrated circuit device to external circuitry. Typically, the contact pads in the array are arranged such that power and ground contact pads are located near the center of the array. Data pins are typically located in various locations throughout the array and are located around the periphery of the array.
This conventional “pin-out” arrangement works well for grid array patterns having 1 millimeter pitch or greater and intermediate frequency integrated circuit devices. However, with high frequency and high current integrated circuit devices and smaller pitch grid arrays, this conventional package substrate design may not provide adequate power and ground connectivity for the integrated circuit device to properly function.
More particularly, openings within power planes and ground planes in the package substrate and in the circuit board allow vias to connect to underlying structures. This significantly reduces the contiguous surface area of the ground plane and the power plane under the flip-chip. In addition, vias in the package substrate that connect to signal pins and some vias in the circuit board that connect to signal pins must pass through both the ground plane and the power plane. Isolation rings extend around these microvias to prevent noise that can disrupt the data signals. Though the isolation rings are effective for noise reduction, they further reduce the size of the ground plane and the size of the power plane.
As a result of the aforementioned reduction in surface area of power and ground planes under the flip-chip, in packages having a high pin count and small-pitch there may not be enough contiguous power plane area and ground plane area to effectively couple power and ground to the integrated circuit device. Moreover, the reduced surface area increases the impedance of the interconnect path. This increased impedance can render the flip-chip integrated circuit device inoperable in high frequency, high current applications.
Accordingly, there is a need for a method and apparatus that will allow for effectively coupling power and ground to flip-chip integrated circuit devices.